| ~Get Your Files Here !/12. Processor Design and its VHDL/1. Simple Processor Design and its VHDL.mp4 | 466.35 MB |
| ~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1. Multiplexers and Shannon Expansion.mp4 | 308.1 MB |
| ~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1. VHDL for adders, Multiplier.mp4 | 293.82 MB |
| ~Get Your Files Here !/11. VHDL code of the bus design with SWAP operation/1. VHDL code of the bus design with SWAP operation.mp4 | 227.82 MB |
| ~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1. HA FA RCA CLA.mp4 | 200.13 MB |
| ~Get Your Files Here !/7. Conditional statement generate statement/1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.mp4 | 196.28 MB |
| ~Get Your Files Here !/6. Decoders Arithmetic Comparator Selected signal assignment/1. Decoders, Arithmetic Comparator, Selected signal assignment.mp4 | 190.21 MB |
| ~Get Your Files Here !/13. Modelsim/3. Modelsim Tutorial 2.mp4 | 189.48 MB |
| ~Get Your Files Here !/9. VHDL gated latches flipflops, registers and counter/1. VHDL for Latches, FlipFlops, registers and counters.mp4 | 158.36 MB |
| ~Get Your Files Here !/10. VHDL parallel load counters and bus design/1. Parallel Load counters and bus design.mp4 | 155.91 MB |
| ~Get Your Files Here !/1. Introduction/1. Introduction to CAD tools.mp4 | 145.36 MB |
| ~Get Your Files Here !/13. Modelsim/2. Modelsim Tutorial 1.mp4 | 128.39 MB |
| ~Get Your Files Here !/8. latches flipflops shift and parallel access registers/1. Latches, FlipFlops, parallel access and shift registers.mp4 | 116.4 MB |
| ~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/2. LUTs, PLDs, FPGA.mp4 | 111.15 MB |
| ~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/1. Numbers Representations.mp4 | 88.86 MB |
| ~Get Your Files Here !/1. Introduction/1.1 Fundamentals Of Digital Logic With VHDL Design 3rd Edition.pdf | 12.16 MB |
| ~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1.1 CENG335 Lecture 2 VHDL Adders Multiplier Narrated.pptx | 3.26 MB |
| ~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1.1 CENG335 Lecture 3 HA FA RCA CLA.pptx | 2.86 MB |
| ~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1.1 CENG335 Lecture 4 Multiplexers and Shannon Expansion.pptx | 2.44 MB |
| ~Get Your Files Here !/12. Processor Design and its VHDL/1.6 Exercises_set1_solution_part2.pdf | 2.37 MB |
| ~Get Your Files Here !/7. Conditional statement generate statement/1.1 CENG335 Lecture 6 conditional statement generate statement.pptx | 2.15 MB |
| ~Get Your Files Here !/12. Processor Design and its VHDL/1.1 CENG335 Lecture 11 Processor Design and its VHDL - Narrated.pptx | 2.05 MB |
| ~Get Your Files Here !/12. Processor Design and its VHDL/1.7 Exercises_Set2_Solution_TTH.pdf | 1.99 MB |
| ~Get Your Files Here !/9. VHDL gated latches flipflops, registers and counter/1.1 CENG335 Lecture 8 vhdl gated latches flipflops, registers and counters.pptx | 1.89 MB |
| ~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/1.1 Lecture 2 - Numbers Repreentation.pptx | 1.81 MB |
| ~Get Your Files Here !/6. Decoders Arithmetic Comparator Selected signal assignment/1.1 CENG335 Lecture 5 Decoders Arithmetic Comparator Selected signal assignment.pptx | 1.71 MB |
| ~Get Your Files Here !/10. VHDL parallel load counters and bus design/1.1 CENG335 Lecture 9 vhdl parallel load counters and bus design - Narrated.pptx | 1.35 MB |
| ~Get Your Files Here !/12. Processor Design and its VHDL/1.5 Exercises_set1_solution_part1.pdf | 1.05 MB |
| ~Get Your Files Here !/8. latches flipflops shift and parallel access registers/1.1 CENG335 Lecture 7 latches flipflops shift and parallel access registers.pptx | 998.24 KB |
| ~Get Your Files Here !/11. VHDL code of the bus design with SWAP operation/1.1 CENG355 Lecture 10 vhdl code of the bus design with swap operation - Narrated.pptx | 953.39 KB |
| ~Get Your Files Here !/1. Introduction/1.2 Lecture 1-Introduction to CAD-VHDL-Ch2_ v3.pptx | 870.93 KB |
| ~Get Your Files Here !/12. Processor Design and its VHDL/1.2 CENG335-Exercises-Set1.pdf | 671.02 KB |
| ~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/2.1 Lecture 2-PLDs- FPGA-Ch3 .pptx | 297.44 KB |
| ~Get Your Files Here !/12. Processor Design and its VHDL/1.3 CENG335-Exercises-Set2.pdf | 191.57 KB |
| ~Get Your Files Here !/12. Processor Design and its VHDL/1.4 CENG335-Exercises-Set3.pdf | 179.25 KB |
| ~Get Your Files Here !/12. Processor Design and its VHDL/1. Simple Processor Design and its VHDL.srt | 84.71 KB |
| ~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1. Multiplexers and Shannon Expansion.srt | 70.52 KB |
| ~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1. VHDL for adders, Multiplier.srt | 47.11 KB |
| ~Get Your Files Here !/6. Decoders Arithmetic Comparator Selected signal assignment/1. Decoders, Arithmetic Comparator, Selected signal assignment.srt | 42.52 KB |
| ~Get Your Files Here !/11. VHDL code of the bus design with SWAP operation/1. VHDL code of the bus design with SWAP operation.srt | 38.88 KB |
| ~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1. HA FA RCA CLA.srt | 38.74 KB |
| ~Get Your Files Here !/10. VHDL parallel load counters and bus design/1. Parallel Load counters and bus design.srt | 37.23 KB |
| ~Get Your Files Here !/7. Conditional statement generate statement/1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.srt | 36.29 KB |
| ~Get Your Files Here !/9. VHDL gated latches flipflops, registers and counter/1. VHDL for Latches, FlipFlops, registers and counters.srt | 33.89 KB |
| ~Get Your Files Here !/8. latches flipflops shift and parallel access registers/1. Latches, FlipFlops, parallel access and shift registers.srt | 33.8 KB |
| ~Get Your Files Here !/1. Introduction/1. Introduction to CAD tools.srt | 29.54 KB |
| ~Get Your Files Here !/13. Modelsim/3. Modelsim Tutorial 2.srt | 28.42 KB |
| ~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/2. LUTs, PLDs, FPGA.srt | 25.41 KB |
| ~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/1. Numbers Representations.srt | 24.57 KB |
| ~Get Your Files Here !/13. Modelsim/2. Modelsim Tutorial 1.srt | 19.32 KB |